The invention relates to a cache memory which permits a higher clock frequency in a processing unit than the maximum permissible clock frequency on the basis of the properties of external memory modules and of the printed circuit board. Cache memories in conventional processor structures, such as in the Motorola MO68040, generally permit only one individual data word to be accessed per clock cycle. In the case of two-dimensional data fields, such as images, this means that a plurality of clock cycles are required to read an image section out of the cache memory if the required pixels do not happen to be situated next to one another in a data word, specifically even when all the data is already present in the cache. IEEE Journal of Solid State Circuit, Vol. 25, No. 3, June 1990 discloses on-chip memories having a plurality of row buffers storing full image rows, pixels situated above one another being read out of row buffers arranged above one another, and pixels which have been read out being transferred to the next row buffer so that they are located at the correct position during the next access operation, which is then carried out shifted by one row. However, this has the disadvantages that the image width is limited by the buffer size, the type of reading is stipulated and column-oriented processing of the image data is not possible without reloading.
It is accordingly an object of the invention to provide a cache memory for two-dimensional data fields which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a cache memory, comprising:
a memory array having data blocks and receiving relatively slow input data and outputting relatively fast output data;
a mapper for flexibly allocating sections within a two-dimensional data field to the data blocks in the memory array, the mapper having an input receiving a request signal and forming from the request signal a write command for a write queue and a read command for a read queue;
a hazard detection unit connected to the mapper for preventing a write control signal from starting a write operation before all read commands in the read queue have been processed whose associated data have already been loaded in the memory array but must not be overwritten yet because the data have not been read from the memory array yet, whereby the hazard detection unit forms a hazard signal from the write commands delayed by the write queue and from addresses from the read queue;
a write controller connected to the hazard detection unit for forming a write control signal for the memory array from the delayed write command and the hazard signal and a synchronization signal; and
a read controller connected to the memory array for forming a read control signal for the memory array from the read signal delayed by the read queue and the synchronization signal, the synchronization signal ensuring that the read control signal is not generated until the required data are present in the memory array.
In accordance with an added feature of the invention, the cache memory has the following further features:
the memory array has memory cells with a first read port, a second read port, and a write port;
the first read port is connected to one of a plurality of vertical read lines and the second read port is connected to one of a plurality of horizontal read lines;
the memory array is split into two separate blocks, with the horizontal read lines in the two blocks being isolated from one another;
the vertical read lines are freely allocatable to the outputs for the output data via a crossbar switch; and
each of the blocks contains diagonally distributed switches between the vertical read lines and the horizontal read lines such that the horizontal read lines can be connected to the crossbar switch via the vertical read lines such that arbitrarily shiftable data field portions are readable with a single access operation.
In accordance with a concomitant feature of the invention, the cache-memory is further characterized by the following advantageous features:
the mapper is configured to form from a request signal write commands and read commands for controlling a given memory array, whereby a request contains a position, a format, and a number for a requested section of a two-dimensional data field, and in which the mapper is configured to check whether all the data in the requested section are already stored in the memory array;
the mapper has mutually isolated data sections which have a portion description with a description of the two-dimensional data field and which can be initialized by means of the request;
the isolated data sections each have two block entries for at least two cache memory blocks in the memory array; and a respective block entry contains a beginning column and a beginning row in a respective section in the two-dimensional data field, a beginning row in the cache memory block, and a number of rows in the respective cache memory block, and also a resident flag indicating whether the cache memory block actually contains valid rows.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a cache memory for two-dimensional data fields, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of the specific embodiment when read in connection with the accompanying drawings.